/*
 * Copyright (c) 2021-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */


#ifndef HPM_TRGMMUX_SRC_H
#define HPM_TRGMMUX_SRC_H

/* trgm0_input mux definitions */
#define HPM_TRGM0_INPUT_SRC_VSS                            (0x0UL)
#define HPM_TRGM0_INPUT_SRC_VDD                            (0x1UL)
#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG                     (0x2UL)
#define HPM_TRGM0_INPUT_SRC_USB0_SOF                       (0x3UL)
#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0                      (0x4UL)
#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1                      (0x5UL)
#define HPM_TRGM0_INPUT_SRC_CMP0_OUT                       (0x6UL)
#define HPM_TRGM0_INPUT_SRC_CMP1_OUT                       (0x7UL)
#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2                    (0x8UL)
#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3                    (0x9UL)
#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2                    (0xAUL)
#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3                    (0xBUL)
#define HPM_TRGM0_INPUT_SRC_TRGM0_P0                       (0x10UL)
#define HPM_TRGM0_INPUT_SRC_TRGM0_P1                       (0x11UL)
#define HPM_TRGM0_INPUT_SRC_TRGM0_P2                       (0x12UL)
#define HPM_TRGM0_INPUT_SRC_TRGM0_P3                       (0x13UL)
#define HPM_TRGM0_INPUT_SRC_TRGM0_P4                       (0x14UL)
#define HPM_TRGM0_INPUT_SRC_TRGM0_P5                       (0x15UL)
#define HPM_TRGM0_INPUT_SRC_TRGM0_P6                       (0x16UL)
#define HPM_TRGM0_INPUT_SRC_TRGM0_P7                       (0x17UL)
#define HPM_TRGM0_INPUT_SRC_SYNT0_CH0                      (0x18UL)
#define HPM_TRGM0_INPUT_SRC_SYNT0_CH1                      (0x19UL)
#define HPM_TRGM0_INPUT_SRC_SYNT0_CH2                      (0x1AUL)
#define HPM_TRGM0_INPUT_SRC_SYNT0_CH3                      (0x1BUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT00                      (0x40UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT01                      (0x41UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT02                      (0x42UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT03                      (0x43UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT04                      (0x44UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT05                      (0x45UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT06                      (0x46UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT07                      (0x47UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT08                      (0x48UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT09                      (0x49UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT10                      (0x4AUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT11                      (0x4BUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT12                      (0x4CUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT13                      (0x4DUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT14                      (0x4EUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT15                      (0x4FUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT16                      (0x50UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT17                      (0x51UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT18                      (0x52UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT19                      (0x53UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT20                      (0x54UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT21                      (0x55UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT22                      (0x56UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT23                      (0x57UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT24                      (0x58UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT25                      (0x59UL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT26                      (0x5AUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT27                      (0x5BUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT28                      (0x5CUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT29                      (0x5DUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT30                      (0x5EUL)
#define HPM_TRGM0_INPUT_SRC_PLB_OUT31                      (0x5FUL)

/* trgm0_output mux definitions */
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_0                  (0x0UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_1                  (0x1UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_2                  (0x2UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_3                  (0x3UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_4                  (0x4UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_5                  (0x5UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_6                  (0x6UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_7                  (0x7UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_0                  (0x8UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_1                  (0x9UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_2                  (0xAUL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_3                  (0xBUL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_4                  (0xCUL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_5                  (0xDUL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_6                  (0xEUL)
#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_7                  (0xFUL)
#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2                    (0x10UL)
#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3                    (0x11UL)
#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI                  (0x12UL)
#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2                    (0x13UL)
#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3                    (0x14UL)
#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI                  (0x15UL)
#define HPM_TRGM0_OUTPUT_SRC_CMP0_WIN                      (0x1CUL)
#define HPM_TRGM0_OUTPUT_SRC_CMP1_WIN                      (0x1DUL)
#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI                    (0x20UL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A                  (0x22UL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B                  (0x23UL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C                  (0x24UL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1A                  (0x25UL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1B                  (0x26UL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1C                  (0x27UL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2A                  (0x28UL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2B                  (0x29UL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2C                  (0x2AUL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3A                  (0x2BUL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3B                  (0x2CUL)
#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3C                  (0x2DUL)
#define HPM_TRGM0_OUTPUT_SRC_CAN_PTPC0_CAP                 (0x2EUL)
#define HPM_TRGM0_OUTPUT_SRC_CAN_PTPC1_CAP                 (0x2FUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_00                     (0x40UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_01                     (0x41UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_02                     (0x42UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_03                     (0x43UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_04                     (0x44UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_05                     (0x45UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_06                     (0x46UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_07                     (0x47UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_08                     (0x48UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_09                     (0x49UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_10                     (0x4AUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_11                     (0x4BUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_12                     (0x4CUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_13                     (0x4DUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_14                     (0x4EUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_15                     (0x4FUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_16                     (0x50UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_17                     (0x51UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_18                     (0x52UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_19                     (0x53UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_20                     (0x54UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_21                     (0x55UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_22                     (0x56UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_23                     (0x57UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_24                     (0x58UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_25                     (0x59UL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_26                     (0x5AUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_27                     (0x5BUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_28                     (0x5CUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_29                     (0x5DUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_30                     (0x5EUL)
#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_31                     (0x5FUL)
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO0                     (0x60UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO1                     (0x61UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2                     (0x62UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO3                     (0x63UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO4                     (0x64UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO5                     (0x65UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO6                     (0x66UL)
#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO7                     (0x67UL)
#define HPM_TRGM0_OUTPUT_SRC_PWM_IN8                       (0x68UL)
#define HPM_TRGM0_OUTPUT_SRC_PWM_IN9                       (0x69UL)
#define HPM_TRGM0_OUTPUT_SRC_PWM_IN10                      (0x6AUL)
#define HPM_TRGM0_OUTPUT_SRC_PWM_IN11                      (0x6BUL)
#define HPM_TRGM0_OUTPUT_SRC_PWM_IN12                      (0x6CUL)
#define HPM_TRGM0_OUTPUT_SRC_PWM_IN13                      (0x6DUL)
#define HPM_TRGM0_OUTPUT_SRC_PWM_IN14                      (0x6EUL)
#define HPM_TRGM0_OUTPUT_SRC_PWM_IN15                      (0x6FUL)
#define HPM_TRGM0_OUTPUT_SRC_SYNCTIMER_TRIG                (0x7EUL)
#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG0                    (0x83UL)
#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG1                    (0x84UL)
#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ0                     (0x85UL)
#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ1                     (0x86UL)
#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA0                     (0x87UL)
#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA1                     (0x88UL)

/* trgm0_filter mux definitions */
#define HPM_TRGM0_FILTER_SRC_TRGM_IN0                      (0x10UL)
#define HPM_TRGM0_FILTER_SRC_TRGM_IN1                      (0x11UL)
#define HPM_TRGM0_FILTER_SRC_TRGM_IN2                      (0x12UL)
#define HPM_TRGM0_FILTER_SRC_TRGM_IN3                      (0x13UL)
#define HPM_TRGM0_FILTER_SRC_TRGM_IN4                      (0x14UL)
#define HPM_TRGM0_FILTER_SRC_TRGM_IN5                      (0x15UL)
#define HPM_TRGM0_FILTER_SRC_TRGM_IN6                      (0x16UL)
#define HPM_TRGM0_FILTER_SRC_TRGM_IN7                      (0x17UL)

/* trgm0_dma mux definitions */
#define HPM_TRGM0_DMA_SRC_TRGM0                            (0x3CUL)
#define HPM_TRGM0_DMA_SRC_TRGM1                            (0x3DUL)



#endif /* HPM_TRGMMUX_SRC_H */
